Please download/print the BUSS Symposium Final Program and review the extended Advance Program below. Registration is closed.
| THURSDAY, 2 May 2024 | ||
| Time | Speaker | Title |
| 8:00 AM |
Registration Opens; coffee/tea | |
| 8:30 AM |
 Habib Hichri, Ajinomoto Fine-Techno USA |
Welcome, Remarks |
| 8:45 AM |
 Dan Berger, NAPMP Associate Director, NIST |
Keynote Talk: NAPMP Plans & Advanced Substrate Onshoring — Packaging has evolved from the role of primarily protecting the chip to one of overall system integration of heterogeneous chiplets. An important aspect of this integration is miniaturization. Feature sizes such as substrate wiring pitch, die-to-substrate bonding pitch, and inter-die distances need to shrink … (more …) |
| 9:30 AM |
 Dr. Dyi-Chung Hu, Founder, SiPlus |
Keynote Talk: 2.xD Integrated Substrate Solutions for High-Performance Computing — The progress of high-performance computing drives the high integration of systems. The industry’s heterogeneous integration solutions are moving in two directions. The first is the integration of dies — examples are HBMs and M1300 die integration. The other direction is substrate integration. High-density … (more) |
| 10:15 AM |
Networking and small-group gatherings Coffee and Tea | |
| 11:00 AM |
Session: Substrate Manufacturing and Onshoring Session Chair: Rozalia Beica, LQDX | |
| 11:00 AM |
 Meredith LaBeau, PhD, Chief Technology Officer, Calumet |
Onshoring Organic Substrates (High-Density Build-Ups): A Tale of Domestic Manufacturing and Title 3 Investments Calumet Electronics is spearheading one of the first domestic capabilities for innovative organic substrates for semiconductors used in Advanced Packaging (AP) to enable overmatch technologies for the Defense Industrial Base, along with commercial customers, bringing along sustainable solutions within a three year period of performance. HDBU Substrates are becoming an essential part of 6th-Generation weapons systems, radar, electronic warfare, processing, communications applications, and advanced packaging … (more) |
| 11:20 AM |
 Michael Gleason, GreenSource Fabrication |
DPA Title III Expansion Update Given the lack of organic ICS capability in the US, and fueled by the demand signals coming for the DIB, Greensource Fabrication has committed to standing up a high mix/low volume heavily automated ICS line. GSF is already supporting the DIB by delivering HDBU hardware utilizing mSAP processes flows with micro-thin foils. With the DPA Title III Technology Investment Agreement won in December 2023 … (more) |
| 11:40 PM |
 Sung Jin Kim, Ph.D., CTO, Absolics |
Packaging Substrate Solutions for Advanced Packaging Requirements The semiconductor industry is indeed undergoing a transformative phase, and advanced packaging technologies play a pivotal role in addressing the evolving demands of microelectronics. Let’s delve deeper into this fascinating field Advanced packaging is now gaining momentum as the next breakthrough in semiconductor technology. Unlike the conventional equipment used for packaging wafers, advanced packaging leverages sophisticated technology to aggregate components from various wafers… (more) |
| 12:00 PM |
 Sundar Kamath, CTO, Sanmina |
An American PCB Manufacturer’s Perspective on the Domestic Substrates Manufacturing Opportunity Sanmina is a leader in high end PCB manufacturing with a 40 year successful history of onshore PCB and electronics manufacturing in the US, Mexico and Canada. and more recently, advanced packaging and silicon photonics capabilities. We have a presence in 8 US States which includes over 1M sq ft of manufacturing right here in Silicon Valley. We also happen to be one of the most vertically integrated electronics manufacturers in North America, supporting high reliability, mission critical markets … (more) |
| 12:20 | Lunch: Fantastic food catered by DishDash Middle Eastern Cuisine | |
| 1:30 PM |
Session: Substrate Materials Session Chair: Dr. Annette Teng, AIM Photonics | |
| 1:30 PM |
 Yoshio Nishimura, Ajinomoto |
Advanced Insulating Material for Next-Generation Package The build-up process is a highly effective method for miniaturization and high-density integration of printed circuit boards. Along with increasing demands for high transmission speed of electronic devices with high functionality, packaging substrates installed with semiconductors in such devices are strongly required to reduce the transmission loss … (more) |
| 1:50 PM |
 Masato Fukui, Resonac |
Substrate Materials for Advanced Packaging The development of advanced packaging technology has been accelerated, such as for 2.5D packaging and chiplet design. Advanced packaging requires HSIO, high density interconnection and large form factor. This motivation for future packaging is the driving force behind the development of substrate materials to meet these challenges. Substrates with superior physical properties … (more) |
| 2:10 PM |
 Hikaru Mizuno, JSR Micro, Inc |
Novel Low Loss Materials for Advanced IC Packaging IC-Substrates and Printed Circuit Boards (PCBs) are high-performing specialty components that consist of organic and inorganic materials. As high-speed communication technologies such as 5G and 6G evolve, IC-Substrate and PCB designs require low loss dielectric materials that decrease loss at high frequency and achieve high signal speed. Additionally, these designs require low CTE materials that achieve low warpage as well as superior reliability … (more) |
| 2:30 PM |
 Yuta Ogawa, Taiyo Ink |
Taiyo’s Photo-Dielectric for High Density Substrate Applications The increasing demand for miniaturization and performance enhancement in microelectronic devices has led to the development of advanced packaging technologies, pushing the limits of IC substrate technologies. Build-up dielectric material play a crucial role in interconnecting various functional units within the packaging, especially in chiplet technology where multiple semiconductor dies are integrated into a single package … (more) |
| 2:40 PM |
Session: Emerging Substrate Technologies Session Chair: Steven Verhaverbeke, Applied Materials | |
| 2:50 PM |
 Steven Verhaverbeke, Applied Materials |
Wafer Level Substrates: An Emerging New Technology The Chiplet revolution needs many chiplets to be assembled at very small pitch on a large substrate and interconnected at high density. Currently the industry approach has been to insert a Si (Wafer Level) Interposer or a RDL Interposer (Wafer Level RDL Interposer) on top of a (Panel Level) Substrate but introduces additional levels of interconnect with additional parasitics. This hinders the adoption of the chiplet revolution … (more) |
| 3:10 PM |
  Vineeth Harish, UCLA, and Prof. Ken Yang, UCLA |
Chiplet Integration on Organic Buildup with Silicon Interconnect Fabric Silicon interconnect fabric (Si-IF) has been shown to be an effective chiplet assembly technology for wafer-scale systems. Dense chiplet placement (<20um) and high density (down to 5um pitch) die-wafer pillar attachments have been demonstrated using thermal compression bonding (TCB). This talk reviews the approach and briefly describes an extension beyond purely silicon-based substrates to interface with organic buildups. These buildups enable wafer-scale integration … (more) |
| 3:35 PM |
 Farhang Yazdani, CEO, BroadPak Corp. |
Advanced X64 UCIe Interface Implementation on a Substrate The integration of chiplets into computing systems has emerged as a pivotal strategy for enhancing performance and scalability. However, traditional methods such as 2.5D interposer integration pose challenges in terms of performance, cost, reliability, and scalability. The integration of the X64 Advanced UCIe interface onto emerging wafer-level substrates represents a significant leap forward in computing architecture, offering a novel alternative to the conventional 2.5D interposer integration approach … (more) |
| 3:55 PM |
Networking and small-group gatherings Coffee and Tea | |
| 4:30 PM |
Panel Moderator: Jan Vardaman, TechSearch International, Inc. | Panel: Substrate Needs: The User Perspective, with panelists Sai Boyapati, Senior Director Advanced Packaging, AMD; Diane Peng, Marvell; Jon Woodyard, Principal Engineer, Microsoft; Omar Bchir, Qualcomm; and Susan Bagen, Microelectronics Consultant, Raytheon. |
| 5:30 PM |
Reception and Networking; dinner catered by Armadillo Willy’s Texas BBQ (dinner: 6:00 – 7:00 PM) | |
| FRIDAY, 3 May 2024 | ||
| Time | Speaker | Title |
| 9:00 AM |
 Venky Sundaram, 3D System Scaling |
Keynote Talk: USA Landscape for Substrate Manufacturing (to be posted) |
| 9:35 AM |
Rahul Iyer, KCK Group | Keynote Talk: Financing and Venture Capital |
| 10:10 AM |
Networking and small-group gatherings Coffee and Tea | |
| 10:40 AM |
Session: Panel Equipment for Substrates Session Chair: Kuldip Johal, Atotech | |
| 10:40 AM |
 Kyle Baker, MKS Instruments |
QCW CO2 Laser Drilling for FCBGA Applications Flip chip ball grid array (FCBGA) package substrate components provide the critical building blocks for electronic devices and high-performance computers. They will enable the future of supercomputing, artificial intelligence processing, autonomous cars, and complex semiconductor modules. Maximizing throughput and quality when drilling vias on materials … (more) |
| 11:00 AM |
 Takuma Yoshikawa, Nikko Materials |
The Latest Vacuum Lamination Challenges and Technology In the growing trend of film material usage and its evolution in IC packaging, there are a number of emerging challenges in vacuum lamination process. In this presentation, we will be introducing our latest technology developments and how we are coping with such issues … (more) |
| 11:20 AM |
 Frank Bruening, MKS Instruments – Atotech |
Systems Solutions for Advanced IC Substrate Manufacturing The surge of interest in Artificial Intelligence (AI) by companies to e.g. enhance customer experience, or revolutionize product development is, next to the private sector, spurring the demand for computing solutions that can support the needed technology nodes. It can be expected that this megatrend will speed up the envisioned technology development of the silicon platforms and the supporting IC substrate infrastructures … (more) |
| 11:40 AM |
 Rozalia Beica, LQDX |
The Future of AI and HPC Substrates: A Breakthrough Interconnect Technology The advancement of artificial intelligence (AI) and high-performance computing (HPC) is bringing a significant change to the semiconductor industry. Central to this progress is the ability to enable high computational and memory needs, driving complexity across the supply chain, including Advanced Packaging and IC substrates. As the sector addresses the demands for the next wave of AI accelerators and HPC Systems … (more) |
| 12:00 PM |
Lunch | |
| 1:00 PM |
Session: Panel Technologies for Substrates Session Chair: Kuldip Johal, Atotech | |
| 1:00 PM |
 Harish Penmethsa, Director Product Marketing, Applied Materials |
Metallization Technologies for Advanced Substrates Copper barrier seed (CuBS) plays a critical role in semiconductor manufacturing processes, including Cu interconnect formation and advanced packaging. Substrate metallization required for 2.5D and 3D packaging entails covering high aspect ratio structures like through-silicon vias (TSVs), interposers, and though-hole vias in advanced substates (e.g., TGV), presenting challenges in devices performance, reliability, production yield, and product cost. Depositing CuBS on panel substrates is essential to achieve high-quality metallization … (more) |
| 1:20 PM |
 Keith Best, Onto Innovation |
The Challenges for Organic and Glass Core Substrates as Advanced Packaging RDL Approaches for 2 µm L/S and Beyond As the Advanced Packaging substrate interconnect density continues to increase rapidly, driven by next generation HPC, AI and VR/AR applications, there has been a paradigm shift in the package architecture to replace organic substrates with glass core substrates. Typically, organic substrates support HVM RDL structures of 9/12 µm line/space and, in R&D, down to 5/5 µm line/space. Beyond this, the substrate’s dimensional stability and flatness will limit the resolution and overlay performance … (more) |
| 1:40 PM |
 Gustavo Ramos, GreeenSource Engineering |
Enhancing Water Quality and Environmental Sustainability in ICS Manufacturing with Zero Liquid Discharge (ZLD) In the current climate of environmental responsibility, it is mandatory for the electronics manufacturing sector to display a clear and committed approach with regards to this topic. This presentation will dive into the key role of Zero Liquid Discharge (ZLD) and closed loop water use in printed circuit boards and IC substrates production, highlighting a unique and patented ZLD system. Specially designed to meet the diverse needs of production, this system is scalable to any volume requirement. … (more) |
| 2:00 PM |
 Saminda Dharmarathna, MacDermid Alpha |
Advanced Electroplating Processes for IC Substrates – Redistribution Layer and Embedded Trenches The rapid developments in the electronics sector have increasingly merged the worlds of printed circuit boards (PCB) and integrated circuit (IC) substrates/semiconductors. This fusion is anchored by the IC substrate, which forms the critical link between IC chips and PCBs, utilizing a network of conductive copper (Cu) traces and vias for connectivity. The advanced IC substrate market is expected to double to $34 billion by 2028, being propelled by the increasing complexity of electronic devices … (more) |
| 2:20 PM |
 Purnima Narayanan, Yield Engineering Systems |
Advanced Packaging Metallization: Substrate Interaction with Catalyst and Electroless Deposition of Copper Advanced packaging scaling introduces high aspect ratio vias (~10:1) where PVD seed layer deposition might be limited. This poses the need to make traditional electroless process feasible on a variety of dielectrics. Success criteria are based on film adhesion with the dielectric, via coverage / throwing power, film resistivity, and Electroless Copper in via to underlying metal contact. Organic build-up film surface plays a vital role … (more) |
| 2:40 PM |
Networking and small-group gatherings Coffee and Tea (short break) | |
| 3:00 PM |
Session: Inspection and Testing (continued) Session Chair: Farhang Yazdani, Broadpak | |
| 3:00 PM |
 Dr Robert Bishop, Beltronics |
Advanced Metrology for High-Density Substrates … |
| 3:20 PM |
 xxx, Tessolve |
xxx … |
| 3:40 PM |
 Orit Hava Armon Hershkovich, KLA EPC-PCB |
Inspection Challenges in ICs and Advanced Panel Packaging Markets ICs and advanced panel substrate key market trends and their impact on panel inspection system requirements … |
| 4:00 PM |
Panel Moderator: Rozalia Beica, LQDX | Panel: Onshoring and Startups: Design, Equipment, Materials, Products, with panelists Sam Salama, founder/CEO, Hyperion, Dr. Siddharth Ravichandran, Chipletz, Brett Sawyer, Nubis Communication, Simon McElrea, CEO, LQDX, Dr. Tristan O. El Bouayadi, CTO, Thintronics, Michael Gleason, GreenSource … |
| 5:00 PM |
Networking — Prize Raffle (must be present to win) | |
| 5:15 PM |
Close of Symposium | |
Panel on Substrate Needs: The User Perspective with five Substrate End Users
Summary: Substrates are required to support high-performance compute and telecom, automotive electronic, consumer, defense, and medical applications. Regardless of the interposer technology, silicon or redistribution layer substrates, attachment to a build-up substrate creates the final package. There is also interest in continuing direct chip attach to a high-density organic substrate, with options including a glass core. This panel provides substrate user perspectives on feature size requirements today and tomorrow. Highlighted is a discussion on requirements to be a substrate supplier in the different applications. Reliability requirements and any special substrate needs are described. Consideration of geographic location for substrate suppliers is addressed.
Session on Emerging Substrate Technologies
Summary: This session will focus on Novel Substrate Technologies that have the potential to bring back Substrate Technologies to the USA. The first talk in this session will introduce Wafer-Level Substrates and contrast this against the current incumbent Panel-Level Substrates with existing installed base in Asia. The second talk in this session will introduce novel substrate finishing structures to enable die bumping on substrates with a <10um pitch. The final talk in this session will introduce novel technologies to enable UCIe connectivity between dies directly on substrates without any Si interposer or RDL interposer.