Wafer Level Substrates – An Emerging New Technology

Steven Verhaverbeke, Applied Materials
ABSTRACT: The Chiplet revolution needs many chiplets to be assembled at very small pitch on a large substrate and interconnected at high density. Currently the industry approach has been to insert a Si (Wafer Level) Interposer or a RDL Interposer (Wafer Level RDL Interposer) on top of a (Panel Level) Substrate but introduces additional levels of interconnect with additional parasitics. This hinders the adoption of the chiplet revolution for wider applications beyond the currently popular integration of GPUs and HBMs. Wafer Level Substrates are emerging as the new platform to enable such wider chiplet revolution by eliminating the extra interconnect levels together with their parasitics. Moreover, this platform enables new thermal cooling solutions and 3-D stacking due to the dual sided access and the capability to embed actives and passives in the Wafer-Level substrate Core.
Steven Verhaverbeke is a Managing Director at Applied Materials. He has been with Applied Materials for 24 years, where he currently leads the activities on Wafer Level Substrates in Applied Materials’ CTO Office. Prior to joining Applied Materials, he was a Director at CFM Technologies, a semiconductor Cleans Equipment maker, from 1995 to 2000, where he was part of the core team that brought the company through an IPO on the Nasdaq. Following going public, CFM was then sold to Mattson, when Steven left the company to join Applied Materials. Prior to joining CFM, Dr. Verhaverbeke was a Research staff member at IMEC, in Leuven, Belgium.
Steven received his Ph. D. from the Catholic University of Leuven in Belgium (KU Leuven) after which he did a post-doc at the Tohoku University in Japan. He has over 100 issued US patents with analogues in other countries and has over 160 publications in Journals and Proceedings. He is also the author of several chapters in 2 books on Wet Etch, Clean and Processing Technologies.

Keynote Talk: NAPMP Plans & Advanced Substrate Onshoring

Dan Berger, NAPMP Associate Director, NIST
Summary: Packaging has evolved from the role of primarily protecting the chip to one of overall system integration of heterogeneous chiplets. An important aspect of this integration is miniaturization. Feature sizes such as substrate wiring pitch, die-to-substrate bonding pitch, and inter-die distances need to shrink in a predictable manner to approach monolithic wiring pitches, last level via pitches and IP block spacings. We refer to this as shrinking down of the package. Simultaneously, we need to increase the number of dies interconnected on the package to improve performance and functionality. We refer to this as scaling out of the package. Current approaches to this include additional levels in the packaging hierarchy with concomitant increases in complexity and cost. We need to think of new ways of flattening the packaging hierarchy by enabling substrates with finer wiring pitches and the ability to assemble dies at fine pitch at high throughput. Besides the technology and processes needed to accomplish this, there are other difficult issues that need to be addressed: these include power delivery and thermal dissipation, high bandwidth, and potentially active wired, wireless, and photonic connectors to the external world or between subsystems. Finally, to make this vision a reality, a chiplet eco system needs to be developed with mechanical and electrical standards that ensure interoperability and a high level of reuse. Similarly, a comprehensive EDA approach needs to be developed that goes well beyond electrical abstraction of the system and includes among other things thermal, thermomechanical considerations, power delivery, test methodology and reliability. This is a challenging opportunity and promises to continue the trend set by Moore’s law, for system integration.
Dan Berger has had his hand in Packaging Development for the last 36 years. After Dan graduated from Purdue in 1988 he joined IBM in East Fishkill New York where he worked until the Microelectronics division was sold to GlobalFoundries in 2015. He continued there until 2022. During that lengthy tenure Dan held numerous management and executive roles in advanced packaging including major transitions such as ceramic to organic substrates, leaded to lead free bumping, single chip modules to multichip modules, Multi-chip modules to 2.5D and 3D stacking solutions, and must recently silicon photonics co-packaged optics. Dan briefly founded a consulting company in advanced packaging in 2023 before receiving the call to join the Chips for America program in NIST as Associated Director of the NAPMP. Dan took on that roll in December of 2023.

Chiplet Integration on Organic Buildup with Silicon Interconnect Fabric

Prof. Ken Yang, UCLA
ABSTRACT: Silicon interconnect fabric (Si-IF) has been shown to be an effective chiplet assembly technology for wafer-scale systems. Dense chiplet placement (<20um) and high density (down to 5um pitch) die-wafer pillar attachments have been demonstrated using thermal compression bonding (TCB). This talk reviews the approach and briefly describes an extension beyond purely silicon-based substrates to interface with organic buildups. These buildups enable wafer-scale integration with through-substrate connections. This marriage enables a high-performance chiplet interconnection fabric with the large-scale manufacturing flexibility of build-up films toward very high performance and high density computing systems.
C.K. Ken Yang graduated with B.S, M.S., and Ph.D. at Stanford University in 1992, 1992, and 1998 respectively. He is a professor at the ECE Department at UCLA since January of 1999 and is currently the Chairman of the Department and the Director (Interim) of UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS). His research interests are in improving the performance and efficiency of digital and mixed-signal circuits. Current research areas include the design of high-speed data and clock-recovery circuits for chip-to-chip interfaces in VLSI systems, analog-to-digital conversion, efficient power generation and delivery for ICs, high-speed digital processing, low-power wireless interfaces, and system architectures to enhance computer networking. He is an IEEE Fellow and a Fellow of AAIA.

Advanced X64 UCIe Interface Implementation on a Substrate

Farhang Yazdani, CEO, BroadPak Corporation
ABSTRACT: The integration of chiplets into computing systems has emerged as a pivotal strategy for enhancing performance and scalability. However, traditional methods such as 2.5D interposer integration pose challenges in terms of performance, cost, reliability, and scalability
The integration of the X64 Advanced UCIe interface onto emerging wafer-level substrates represents a significant leap forward in computing architecture, offering a novel alternative to the conventional 2.5D interposer integration approach. We propose a pioneering methodology for seamlessly integrating the X64 Advanced UCIe interface on emerging wafer-level substrates, eliminating the complexities associated with the 2.5D interposer integration approach. Through meticulous design and optimization strategies, we introduce an innovative approach that leverages the unique advantages of emerging wafer-level substrates, such as improved interconnect density, enhanced signal integrity, and reduced form factor. By directly implementing the X64 Advanced UCIe interface on these substrates, we overcome the limitations of traditional 2.5D interposer integration, including increased complexity, cost, and design challenges. Our findings underscore the transformative potential of eliminating the 2.5D integration approach in favor of direct implementation onto a single substrate, paving the way for the development of next-generation computing systems with unparalleled levels of efficiency, scalability, and reliability.
Farhang Yazdani is the President and CEO of BroadPak Corporation, a provider of advanced 2.5D/3D heterogeneous chiplet integration and co-packaged optics design/manufacturing services based in San Jose, California. Through his 23 years in the industry, he has served in various technical, management, and advisory positions with leading semiconductor companies worldwide. He is the author of the book “Foundations of Heterogeneous Integration: An Industry-Based, 2.5D/3D Pathfinding and Co-Design Approach”. He is the recipient of the 2013 NIPSIA award in recognition of his contribution to the advancement and innovations in packaging technologies. He has numerous publications and IPs in the area of 2.5D/3D Packaging and Assembly, serves on various technical committees, and is a frequent reviewer for the IEEE Journal of Advanced Packaging. He received his undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle.

Enhancing Water Quality and Environmental Sustainability in ICS Manufacturing with Zero Liquid Discharge (ZLD)

Gustavo Ramos, Sr Director Business Development, GreenSource Engineering
ABSTRACT: In the current climate of environmental responsibility, it is mandatory for the electronics manufacturing sector to display a clear and committed approach with regards to this topic.
This presentation will dive into the key role of Zero Liquid Discharge (ZLD) and closed loop water use in printed circuit boards and IC substrates production, highlighting a unique and patented ZLD system. Specially designed to meet the diverse needs of production, this system is scalable to any volume requirement. This attribute makes this production proved solution a robust choice for operations of all sizes and technical complexity. This presentation will endeavor to evaluate the assets of a special closed loop water recycling system to showcase the real-life benefits and achievements to date of this novel approach. With real-life installations as our foundation, we will share compelling data and results that speak to the effectiveness and environmental benefits of our technology in terms of industry applicable water in a volume that satisfies production volume.
Gustavo Ramos is Sr Director Business Development & Global Sales and Service at GreenSource Engineering. He is chemical engineer graduated at the University of Sao Paulo, Brazil with 20+ years experience on printed circuit board fabrication and assembly. Before that, he worked at MKS-Atotech in the Headquarters in Berlin Germany, where he held several positions in the Electronics Department, lastly as Global Product Director Final Finishing. Among the main responsibilities were the development, marketing and introduction of products and process for the production PCBs and advanced packaging substrates in the electronics industry.

The Latest Vacuum Lamination Challenges and Technology Development

Takuma Yoshikawa, Nikko Materials
ABSTRACT: In the growing trend of film material usage and its evolution in IC packaging, there are a number of emerging challenges in vacuum lamination process. In this presentation, we will be introducing our latest technology developments and how we are coping with such issues.
Takuma Yoshikawa

Advanced Insulating Material for Next-Generation Packaging

Yoshio Nishimura, R&D Group manager, Ajinomoto Co., Inc.
ABSTRACT: The build-up process is a highly effective method for miniaturization and high-density integration of printed circuit boards. Along with increasing demands for high transmission speed of electronic devices with high functionality, packaging substrates installed with semiconductors in such devices are strongly required to reduce the transmission loss. In this presentation, we report advanced insulating materials for those packaging substrates. First, our advanced insulating materials for a semi-additive process (SAP) are introduced. Our materials show low dielectric loss tangent, smooth resin surface by SAP and good reliability to meet the demand of next-generation packages. In addition, build-up materials for thinner dielectric layers and fine line and space (FLS) are developed. They can produce FLS under 3 μm pitch by a semi-additive process and fine vias under 10 μm by a laser drilling process. Evaluation of ABF with glass substrates is introduced.
Yoshio Nishimura has been an R&D engineer at Ajinomoto Co., Inc. for more than 10 years and has worked on insulating materials for packaging substrates.

2.xD Integrated Substrate Solutions for High-Performance Computing

Dr. Dyi-Chung Hu, SiPlus Co.
ABSTRACT: The progress of high-performance computing drives the high integration of systems. The industry’s heterogeneous integration solutions are moving in two directions. The first is the integration of dies — examples are HBMs and M1300 die integration. The other direction is substrate integration. High-density interposers such as CoWoS and EMIB have been used in HPC for many years to reduce the interconnection between chips. However, these solutions are solutions in reducing the interconnection distance between dies in planes for the X and Y directions. Recently, reducing the interconnection distance in the thickness (Z) direction, such as the RDL-based TSV-Less solution, has emerged. The use of coreless (TLV-Less) substrates has been in the market for many years. The combinations of a TSV-less interposer and TLV-less substrate as an integrated substrate solution have been under development for many years. Those are 2.XD solutions.
For the 2.xD solutions, only 2.0D. 2.1D, 2.2D, and 2.3D can provide the benefit of reducing the connection distance between dies in the Z direction. In this talk, the development of 2.xD integration and its application are explained in detail. Combined 2.xD solutions with a glass substrate will provide large flat substrate solutions to meet the HPC demands.
Dr. Dyi-Chung Hu is an expert in semiconductor advanced electronics packaging. He earned a Ph. D. degree from MIT in the Material Science and Engineering Department. He has been one of the pioneers in creating the Taiwan TFT LCD industry and cofounder of two Taiwanese TFT LCD Companies — E-Ink and HannStar Co. He is the founding chairman of SEMICON-Taiwan’s electronics packaging committee. From 2010 to 2014, he was the Senior VP of RD at Unimicron. In 2014, he founded the substrate integration company SiPlus Co. For the past ten years, he has developed 2.0D, 2.1D, 2.2D, and 2.3D structures and processes for integrated substrates for semiconductor heterogeneous integration.
Dr. Hu has contributed substantially to Taiwan semiconductor packaging, TFT LCD, and substrate development and manufacture. He has many invited speeches in advanced substrate and packaging development worldwide. He has over 100 patents in the above fields.

Advanced Metrology for High-Density Substrates

Dr. Robert Bishop, president, Beltronics Inc.
ABSTRACT: (to be provided)
Dr. Robert Bishop is president of Beltronics Incorporated which he founded in 1980. He received his doctorate degrees in electronical engineering and computer science with emphasis on neural network systems from MIT and Harvard in 1980. He holds 27 patents and technologies incorporating advances in ophthalmic scanners, OCT, MRI, and CAT scanners, DNA analysis systems, high speed low light image sensors, optics, lasers, digital signal processing technologies, and AI computer algorithms for analysis of complex images.

Substrate Materials for Advanced Packaging

Masato Fukui, Resonac America
ABSTRACT: The development of advanced packaging technology has been accelerated, such as for 2.5D packaging and chiplet design. Advanced packaging requires HSIO, high density interconnection and large form factor. This motivation for future packaging is the driving force behind the development of substrate materials to meet these challenges. Substrates with superior physical properties can be made thinner while maintaining substrate warpage, thereby enabling fine pitch through-hole and reducing signal loss. To improve manufacturing yields for large size packaging, better coplanarity and dimensional stability in both the planar and thickness directions are required. The latest development status and technical direction for substrate materials will be presented.
Masato Fukui attained his Masters of Engineering degree in Molecular Chemistry and Applied Chemistry from Osaka University’s Graduate School of Engineering. He joined Hitachi Chemical Co Ltd. in 2007, which later became Resonac Corp. He worked as an engineer in the Laminate Materials R&D department. Masa joined Resonac America in October 2022.

Packaging Substrate Solutions for Advanced Packaging Requirements

Sung Jin Kim, Ph.D., CTO, Absolics
ABSTRACT: The semiconductor industry is indeed undergoing a transformative phase, and advanced packaging technologies play a pivotal role in addressing the evolving demands of microelectronics. Let’s delve deeper into this fascinating field Advanced packaging is now gaining momentum as the next breakthrough in semiconductor technology. Unlike the conventional equipment used for packaging wafers, advanced packaging leverages sophisticated technology to aggregate components from various wafers, resulting in single electronic devices with superior performance. Advanced packaging meets the demands of emerging applications that are now going mainstream. Examples include high performance computing, 5G, autonomous vehicles, and virtual/augmented reality. These applications require high-performance, low-power chips capable of processing massive data quantities. Despite Moore’s Law predicting the doubling of transistors on a microchip every few years, node advancement is reaching its limits. Technical advances in front-end chip manufacturing are slowing down, and the economically viable maximum die size is becoming more restricted. 3D-Heterogeneous Integration combines different functional chips within a single package. Absolics, with its advanced packaging fab in Georgia, is poised to revolutionize the industry. Industry adoption of this innovative product will pave the way for additional breakthroughs, harnessing the unique material properties of glass. Advanced packaging is the bridge to overcoming the limitations of traditional scaling, and glass core substrates exemplify the cutting-edge possibilities in this field. Throughout the presentation, major technical and business insights will be shared for the following three fundamental questions regarding glass core substrate products: 1. How did we get here? 2. What does tomorrow bring? And lastly, 3. Are we alone?
Dr. Sung Jin Kim is the CTO of Absolics, a recently spun-off semiconductor packaging business from SK Group in the USA. With 29 years of experience in the semiconductor and microelectronics packaging industry, Dr. Kim leads new technology and business development for advanced semiconductor packaging solutions at Absolics. Prior to Absolics, he held executive positions in various companies and countries, including SKC, Georgia Institute of Technology, Foxconn Advanced Technology, Daeduck Electronics, UTAC, and Amkor Technology. Throughout his career, Dr. Kim managed package engineering, substrate manufacturing, and embedding component microelectronic package engineering. He has over 100 US patents and holds a doctorate in electrical engineering from the Technical University of Dresden, Germany.

QCW CO2 Laser Drilling for FCBGA Applications

Kyle Baker, MKS Instruments
ABSTRACT: Flip chip ball grid array (FCBGA) package substrate components provide the critical building blocks for electronic devices and high-performance computers. They will enable the future of supercomputing, artificial intelligence processing, autonomous cars, and complex semiconductor modules. Maximizing throughput and quality when drilling vias on materials and applications used to produce these components, within a high-volume manufacturing process, has become challenging with current and future specifications.
Current generation laser via drilling systems are capable, but not productive enough for the increasing throughput needs of the top substrate suppliers. Therefore, a laser via drilling system that can deliver both constant power and high via quality on ~30-60um vias would help enable and transform new technologies at an accelerated rate. Using a quasi-continuous wave laser (QCW) source enables constant laser power to the work surface, which eliminates the wait time needed for pulse availability on traditional CO2 lasers. Via drilling is no longer restricted to stage or galvanometer move-time limitations.
The combination of a QCW laser, acousto-optic device (AOD) beam-steering and modulation technology will enable a new level of throughput and accuracy for ABF drilling. In this talk, I will discuss the principals and deliverables of this emerging technology (MKS/ESI Geode A – Via Drilling System designed for ABF Materials), and how to harness and manipulate the properties of a QCW laser for maximum efficiency. Laser via formation is a foundational step in the integrated circuit and substrate architecture, and a creative combination of laser and optics can further transform the current processes and alleviate production bottlenecks.

Novel Low Loss Materials for Advanced IC Packaging

Hikaru Mizuno, JSR Micro, Inc
ABSTRACT: IC-Substrates and Printed Circuit Boards (PCBs) are high-performing specialty components that consist of organic and inorganic materials. As high-speed communication technologies such as 5G and 6G evolve, IC-Substrate and PCB designs require low loss dielectric materials that decrease loss at high frequency and achieve high signal speed. Additionally, these designs require low CTE materials that achieve low warpage as well as superior reliability. This presentation introduces a newly designed thermoset material with a low dielectric constant and a low dissipation factor. The cured material shows an ultra-low dissipation factor of 0.0011 at 10GHz, and high adhesion (0.8 N/mm) to a smooth copper surface. The presentation also discusses how material design impacts electrical and mechanical properties for optimal device performance.
Hikaru Mizuno joined JSR Corporation in 2009 and worked in Fine Electronic Materials Research Laboratories. In 2018, he joined JSR Micro, Inc., and has been engaged in research and development of electronic materials. He has submitted 8 papers and 18 patents.

Taiyo’s Photo-Dielectric for High Density Substrate Applications

Yuta Ogawa, Taiyo Ink Manufacturing Co
ABSTRACT: The increasing demand for miniaturization and performance enhancement in microelectronic devices has led to the development of advanced packaging technologies, pushing the limits of IC substrate technologies. Build-up dielectric material play a crucial role in interconnecting various functional units within the packaging, especially in chiplet technology where multiple semiconductor dies are integrated into a single package. This paper presents our dry-film photo-dielectric material tailored specifically for high-density build-up applications. The material offers ultra-small micro-via formation by photolithography processes and fine pitch Cu wiring patterning by standard semi-additive processing (SAP). Additionally, the new photo dielectric material addresses the technical challenges present in conventional liquid polyimide materials, such as high curing temperature and surface unevenness. These superior characteristics makes Taiyo’s photo dielectric an ideal dielectric material for next-generation IC substrates. Experimental results demonstrate the feasibility and advantages of integrating the proposed photo-dielectric into IC substrate manufacturing processes, paving the way for the realization of next-generation electronic devices.
Yuta Ogawa is a senior project manager of Taiyo Ink Mfg. Co., Ltd. He has the B.A in chemistry from Kanagawa institute of technology from in 1996. He started his career as an engineer at Taiyo Ink, and filed more than 10 patents on electronic materials in about 10 years. Then he extended his career in business development within the IC packaging industry, working for more than 10 years in the U.S., Japan, Taiwan, and China.

Advanced Electroplating Processes for IC Substrates – Redistribution Layer and Embedded Trenches

Saminda Dharmarathna, MacDermid Alpha
ABSTRACT: Rapid developments in the electronics sector have increasingly merged the worlds of printed circuit boards (PCB) and integrated circuit (IC) substrates/semiconductors. This fusion is anchored by the IC substrate, which forms the critical link between IC chips and PCBs, utilizing a network of conductive copper (Cu) traces and vias for connectivity. The advanced IC substrate market is expected to double to $34 billion by 2028, being propelled by the increasing complexity of electronic devices, underscored by advancements in GPUs, AI accelerators, and cloud computing technologies. This growth is further amplified by over $15 billion in investments since 2021, reflecting the sector’s dynamic potential and the strategic emphasis on high-density connectivity solutions.
IC substrates are at the forefront of the electronics industry’s drive towards greater miniaturization, higher yield, and lower costs. The quest for minimizing the distance between Cu traces to achieve maximum substrate utilization underscores the industry’s push towards advanced wafer-level technologies with ≤2 µm L/S with strict uniformity within unit (WIU) and within panel (WIP). The emerging challenges and opportunities presented by scale mismatch and smaller L/S distances necessitate innovations like Fan-out panel-level packaging (FOPLP). The development of new plating solutions, focusing on uniformity and planarity, is crucial for overcoming the hurdles in multilayer processing, preventing signal transmission loss, and ensuring the reliability of increasingly complex electronic systems. The integration of cutting-edge additive packages for DC Cu electroplating, emphasizing trench and via filling capabilities, exemplifies the industry’s commitment to pushing the boundaries of IC substrate technology, paving the way for the next generation of electronics manufacturing.
We present two distinct processes for redistribution layer (RDL) and embedded trench plating, two processes that are at the forefront of IC substrate research and manufacturing. RDL processes showed excellent via fil capability and uniformity, while those for embedded trench plate showed great uniformity (for both WIU and WIP) and profile for fine lines. For both processes, the physical properties, tensile strength, and elongation remained stable as the bath aged. Low internal stress was shown for both on plated and annealed samples. The development and optimization of these redistribution layer (RDL) and embedded trench plating processes not only enhance the fabrication quality and reliability of integrated circuit (IC) substrates but also meet the rigorous standards of IPC class III, indicating a significant advancement in IC substrate manufacturing that promises improved performance and durability for electronic devices.

The Future of AI and HPC Substrates: A Breakthrough Interconnect Technology

Rozalia Beica, LQDX
ABSTRACT: The advancement of artificial intelligence (AI) and high-performance computing (HPC) is bringing a significant change to the semiconductor industry. Central to this progress is the ability to enable high computational and memory needs, driving complexity across the supply chain, including Advanced Packaging and IC substrates. As the sector addresses the demands for the next wave of AI accelerators and HPC Systems, ultra-high density interconnects stand out as a key enabler, further driving advancements in IC Substrates to meet the needs of future designs. This presentation will focus on industry trends in interconnects, highlighting LQDX’s cutting-edge metallization technology, a breakthrough interconnect solution depositing atom-by-atom using a flexible and low-cost wet chemistry and process.
Bio: With over 30 years of distinguished leadership in the Semiconductor and Advanced Packaging industry, Rozalia brings a wealth of expertise across electronic materials, substrates, equipment, device & system manufacturing, and market intelligence. Rozalia has held several executive roles in technology development, strategic planning, business development, sales, marketing and operations and has been instrumental in the growth and success of industry giants such as Rohm and Haas, Dow, DuPont, Semitool, Applied Materials, Lam Research, Maxim Integrated Products, Yole Developpement, and AT&S. Recently, Rozalia took on the role of Chief Commercial Officer at LQDX, where she is driving strategic growth.
An active participant in industry activities, Rozalia led numerous symposiums globally, consortia activities, technical working groups and industry roadmaps activities. Rozalia served on the board of IEEE EPS, IMAPS and 3DinCites, currently she is a Member of the Advisory Board at IMPACT and Terecircuits. Additionally, her academic journey includes notable degrees in Chemical Engineering, Management of Technology and Strategy, along with a Global Executive MBA.

Systems Solutions for Advanced IC Substrate Manufacturing

Dr. Frank Bruening, MKS Instruments – Atotech
ABSTRACT: The surge of interest in Artificial Intelligence (AI) by companies to e.g. enhance customer experience, or revolutionize product development is, next to the private sector, spurring the demand for computing solutions that can support the needed technology nodes. It can be expected that this megatrend will speed up the envisioned technology development of the silicon platforms and the supporting IC substrate infrastructures. The expected growth rates 2027/2023 with a CAAGR of +8.5% – especially for FC-BGA and FC-CSP, underline the continued growth expectations (Prismark PCB report Feb 2023), where ICS active areas are projected to reach up to 150 x 150 mm. The mantra of continued miniaturization puts a lot of pressure on the related supply chain, specifically in terms of investments into new or modified infrastructures, while managing yield to keep cost under control. The corresponding talk will highlight state-of-the-art offerings of materials for primary metallization (e.g. Catalysts, Electroless Cu) in conjunction with unique equipment design offerings. This should mostly extend the lifetime of installed wet chemical infrastructure in contrast to costly investments in new dry process alternatives for HVM. The need for safe processability concerning fine line technology (below 5µm L/S) on last generation low roughness built-up film materials without compromising on reliability will be noted.
Dr. Frank Bruening is a General Manager at MKS’s Materials Solutions Division – Atotech. He is responsible for Desmear, Metallization, and Surface Treatment Technologies and their application in Printed Circuit Board (PCB) and IC Substrate (ICS) manufacturing. Frank began his career at Atotech as an Application Engineer over 20 years ago. In this time, he has held multiple positions all of which have been in the electronics division. Frank holds over 10 key patents and has over 40 peer-reviewed publications. His current focus is on the development and application of specialty chemicals and integrated solutions with respect to equipment for current and future applications. Such applications stretch to panel level packaging (PLP) and metallization of glass substrates. Key point areas are system integration, next level reliability of interconnects, and sustainable and environmentally friendly process solutions meeting ESG demands of the global society. Frank earned his doctorate degree in 2000 from the Free University Berlin in the Department of Physical Chemistry with a specialization in negative ion mass spectrometry in ultra-high vacuum environments. He complimented his degree in physical chemistry with a MSc degree in Media Sciences at the Technical University in Berlin in 1996. He has recently certified in Change and Innovation Management at the University of St. Gallen/Switzerland.

The Challenges for Organic and Glass Core Substrates as Advanced Packaging RDL Approaches at 2 µm L/S and Beyond

Keith Best, Onto Innovation
ABSTRACT: Advanced packaging scaling introduces high aspect ratio vias (~10:1) where PVD seed layer deposition might be limited. This poses the need to make traditional electroless process feasible on a variety of dielectrics. Success criteria are based on film adhesion with the dielectric, via coverage / throwing power, film resistivity, and Electroless Copper in via to underlying metal contact. Organic build-up film surface plays a vital role in the adhesion of copper deposited using electroless deposition process. In this work we are studying the impact of different surface treatment/roughening processes on the adhesion of Electroless copper. This is also coupled with alternate catalysts and their coverage/ composition on the build-up layers. With initial results suggesting basic via fill capability, the primary challenge remains in Eless Cu to build up film adhesion improvement.
Bio: For more than 35 years, Keith Best has held a range of semiconductor processing and applications positions for both device manufacturing and capital equipment companies, of which 13 years were with ASML where he held the position of Director, Applications Engineering. Most recently, Keith was Advanced Packaging Process Development Engineering Manager at SkyWater Florida. He is currently the Director of Product Marketing, Lithography, at Onto Innovation supporting the JetStep® advanced packaging lithography stepper. Keith holds a B.Sc. Honors Degree in Materials Science from the University of Greenwich, UK. He has numerous publications and holds 22 US patents in the areas of photolithography and process integration.

Onshoring Organic Substrates (High-Density Build-Ups): A Tale of Domestic Manufacturing and Title 3 Investments

Meredith LaBeau, PhD, Chief Technology Officer, Calumet
ABSTRACT: Calumet Electronics is spearheading one of the first domestic capabilities for innovative organic substrates for semiconductors used in Advanced Packaging (AP) to enable overmatch technologies for the Defense Industrial Base, along with commercial customers, bringing along sustainable solutions within a three year period of performance. HDBU Substrates are becoming an essential part of 6th-Generation weapons systems, radar, electronic warfare, processing, communications applications, and advanced packaging. In a relatively short timeframe, Calumet Electronics will enable DoD primes to build overmatch technologies in the United States, while attracting and growing the workforce with needed industrial skills to support the DoD in the national defense. Calumet’s pure play approach towards solving tough industry challenges will support U.S. defense primes, removing restrictions imposed by offshore manufacturers, and enabling innovative, leap-ahead technologies and overmatch capability. The Title 3 investment is rapidly advance domestic capabilities to fabricate production-grade HDBU Substrates. This talk will showcase the progress of on-shoring and support of government investments to begin to secure a supply chain in the United States.
Meredith Ballard LaBeau is the Chief Technology Officer (CTO) and on the strategic leadership team at Calumet Electronics, a leader in manufacturing high-performance Printed Circuit Boards (PCBs) and IC Substrates for defense, aerospace, medical, power-grid, commercial, industrial controls, and space applications. She is the technical lead and manager of Calumet’s Process Engineering and R&D teams. She also is a member of two international standards committees: IPC and the National Aerospace and Defense Contractors Accreditation Program (NADCAP), an IPC Board Member and plays a critical role in developing standards and PCB manufacturing quality and criteria for the electronics industry. Meredith was recently elected to serve as an inaugural member of the Industrial Advisory Committee for CHIPs for America, providing advice on science and technology needs of the nations’ domestic microelectronics industry.
Meredith received her PhD from Michigan Technological University in Environmental Engineering focusing on the integrated assessment of anthropogenic, climate and policy induced changes on phosphorus export in the United States Laurentian Great Lakes watersheds. Meredith’s education includes a masters’ degree from Michigan Tech in environmental engineering for the performance and systems analysis of wastewater treatment systems and potable water in rural Bolivia. During her academic career, Meredith earned awards for S-STEM research, integrative graduate education and research traineeship, international sustainable development, 1st runner-up for best student paper at the International Association of Great Lakes Research and a summer Vespucci institute scholar. She currently holds 5 publications focused on watershed research, phosphorus, and the Great Lakes. Prior to the advanced degrees, Meredith completed a bachelors’ degrees in biomedical engineering, also from Michigan Tech.

Advanced Packaging Metallization: Substrate Interaction with Catalyst and Electroless Deposition of Copper

Purnima Narayanan, Yield Engineering Systems
Abstract: Advanced packaging scaling introduces high aspect ratio vias (~10:1) where PVD seed layer deposition might be limited. This poses the need to make traditional electroless process feasible on a variety of dielectrics. Success criteria are based on film adhesion with the dielectric, via coverage / throwing power, film resistivity, and Electroless Copper in via to underlying metal contact. Organic build-up film surface plays a vital role in the adhesion of copper deposited using electroless deposition process. In this work we are studying the impact of different surface treatment/roughening processes on the adhesion of Electroless copper. This is also coupled with alternate catalysts and their coverage/ composition on the build-up layers. With initial results suggesting basic via fill capability, the primary challenge remains in Electroless Cu to build up film adhesion improvement.

Metallization Technologies for Advanced Substrates

Harish V Penmethsa, Director Product Marketing, Applied Materials
ABSTRACT: Copper barrier seed (CuBS) plays a critical role in semiconductor manufacturing processes, including Cu interconnect formation and advanced packaging. Substrate metallization required for 2.5D and 3D packaging entails covering high aspect ratio structures like through-silicon vias (TSVs), interposers, and though-hole vias in advanced substates (e.g., TGV), presenting challenges in devices performance, reliability, production yield, and product cost. Depositing CuBS on panel substrates is essential to achieve high-quality metallization in TGV and buildup layers with continuous coverage and strong adhesion. Physical vapor deposition (PVD) is widely employed for depositing CuBS on high aspect ratio vias in advanced packaging and is further recognized as a promising technology for panel-level metallization due to its capability to offer continuous coverage, low resistivity, and strong adhesion. In addition, panel handling poses one of the key challenges in production, primarily due to limited keep-out-zone (KOZ) for panel contacts and varying levels of warpage induced by large panel size, reduced thickness, materials variations (e.g., organic vs glass), and film stress. Moreover, controlling panel temperature during deposition process is crucial for achieve high yield and metallization quality. Applied Materials Topaz™ PVD system with cluster chamber architecture is capable of handling substrates up to 600x600mm and supporting multiple applications (RDL, TGV, Dielectric, BSM). CuBS step coverage and adhesion to glass is optimized based on glass type and TGV profile. Topaz patented cooling technology can monitor and control temperature on both organic and glass substrates. The throughput of the system is significantly enhanced by vacuum flipping capability of the system which eliminates additional degas, pump down and pre-clean steps. Applied Materials Topaz™ PVD system creates an industry ecosystem for semiconductor-grade panel-level packaging.
Harish Penmethsa is Director of Product marketing in Heterogeneous Integration Group.
Harish has more than 15 years of experience in semiconductor equipment industry and joined AppliedMaterials in 2021 following the acquisition of Tango Systems, where he led engineering and product support for PVD products. He has over 10 years’ of experience working on capital equipment and process integration for substrate technologies. He holds a master’s degree in Mechanical design from San Jose State University and B.Tech in Mechanical Engineering from Anna University.

An American PCB Manufacturer’s Perspective on the Domestic Substrates Manufacturing Opportunity

Sundar Kamath, CTO & Sr. VP, Sanmina
Abstract: Sanmina is a leader in high end PCB manufacturing with a 40 year successful history of onshore PCB and electronics manufacturing in the US, Mexico and Canada. and more recently, advanced packaging and silicon photonics capabilities. We have a presence in 8 US States which includes over 1M sq ft of manufacturing right here in Silicon Valley. We also happen to be one of the most vertically integrated electronics manufacturers in North America, supporting high reliability, mission critical markets such as Defense & Aerospace. Given this stable domestic foundation of hi-tech manufacturing in the US, it would seem logical for Sanmina to consider build-up substrate manufacturing as the next phase of growth, to align with, and support the silicon foundries expected to be operational in the next 3 years or so. However, there are numerous open questions – how do we address the gaps in materials, process technologies, equipment, infrastructure, skilled resources and know-how which exist within the still nascent US ecosystem for build up substrate manufacturing? Can we manufacture at an acceptable cost in the US? With so much foundry capacity coming on stream, for a relatively contained set of US customers, what volumes and demand scenarios make sense? Is the substrate business model viable given the capex needs? Will the business model survive if and when overseas low cost suppliers are able to export to the US market? Can we consider public-private partnerships or consortia to offset the business risks? These and related issues must be analyzed and addressed for a successful substrate industry to emerge in the US.
Sundar Kanath has over 24 years of executive management experience, leading product development and technology teams at Sanmina, a global leader in integrated manufacturing solutions. He managed the realization of high-tech products for various industry verticals, from concept design to manufacturing launch, leveraging expertise in design and development, microelectronics, semiconductor device packaging, interconnects, assembly, electro-mechanical systems, etc. His current focus mainly on clean energy initiatives, US domestic microelectronics, India electronics manufacturing growth market. His leadership and technical experience covers multiple functions: product, technology and process development and roadmaps, ODM products, new product introduction, prototyping and manufacturing launch, global design centers (P&L), manufacturing and applications engineering, product marketing, go to market, and strategic M&A. Sundar has a strong track record of driving innovation, collaboration, and growth plans for emerging tech (optical, wireless, cleantech), 12 issued patents, multiple publications, keynotes, and board memberships. Passionate about building US-India technology ventures, Silicon Valley start-ups, social impact startups, and applying appropriate technology solutions to develop under-served and rural communities (Ideal Village program).

DPA Title III Expansion Update

Michael Gleason, Director of Product Development & Strategic Growth, GreenSource Fabrication
ABSTRACT: Given the lack of organic ICS capability in the US, and fueled by the demand signals coming for the DIB, Greensource Fabrication has committed to standing up a high mix/low volume heavily automated ICS line. GSF is already supporting the DIB by delivering HDBU hardware utilizing mSAP processes flows with micro-thin foils. With the DPA Title III Technology Investment Agreement won in December 2023, GSF will push into pure SAP manufacturing process flows utilizing build-up films to achieve even greater densities and higher resolution features to support the needs of the quickly progressing Advanced Packaging platforms. GSF will be presenting an update on their progress.
Michael Gleason is the Director of Product Development and Strategic Growth for GreenSource Fabrication in Charlestown, New Hampshire. Mike’s 18-year career in the PCB manufacturing industry has established him as a distinguished expert in electronics design and fabrication. He has held management and executive positions in operations, engineering and business development across multiple US fabricators supporting the needs of the DoD. Prior to joining GSF, Mike spent 5 years at Draper, leading advanced initiatives in bleeding-edge PCB designs, UHDI, organic substrates, and Substrate Like PCBs, notably advancing anti-tamper electronics packaging. Mike’s deep expertise and innovative leadership have been pivotal in driving GSF’s technical roadmap. Mike studied mechanical engineering and has a B.S. in Operations Management from the University of New Hampshire.